View 73K321L-IH_804507.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

73K321L CCITT V.23, V.21 Single-Chip Modem
April 2000
DESCRIPTION
The 73K321L is a highly integrated single-chip modem IC which provides the functions needed to construct a CCITT V.23 and V.21 compatible modem, capable of 0-300 bit/s full-duplex or 0-1200 bit/s half-duplex operation over dial-up telephone lines. The 73K321L provides 1200 bit/s operation in V.23 mode and 300 bit/s in V.21 mode. The 73K321L also can both detect and generate the 2100 Hz answer tone needed for call initiation. The 73K321L integrates analog, digital, and switchedcapacitor array functions on a single substrate, offering excellent performance and a high level of functional integration in a single 28-pin DIP or PLCC package. The 73K321L operates from a single +5V supply with very low power consumption. The 73K321L includes the FSK modulator/demodulator functions, call progress and handshake tone monitor test modes, and a tone generator capable of producing DTMF, answer, calling tones. The 73K321L is designed to appear to the systems designer as a microprocessor peripheral, and will easily interface with popular onechip microprocessors (80C51 typical) for control of modem functions through its 8-bit multiplexed address/data bus or via an optional serial control bus. An ALE control line simplifies address demultiplexing. Data communications occurs through a separate serial port only.
(continued)
FEATURES
* * One-chip CCITT V.23 and V.21 standard compatible modem data pump Full-duplex operation at 0-300 bit/s (V.21) or 0-1200 bit/s ( .23) forward channel with or V without 0-75 bits/s back channel Full Duplex 0-1200 bit/s (V.23) in 4-wire mode Pin and software compatible with other TDK Semiconductor Corporation K-Series 1-chip modems Interfaces directly with standard processors (8048, 80C51 typical) Serial port for data transfer Call progress, carrier, precise answer tone (2100 Hz), calling tone (1300 Hz) and FSK mark detectors DTMF generator Test modes available: ALB, DL, RDL, Mark, Space, Alternating bit patterns Precise automatic gain control allows 45 dB dynamic range CMOS technology for low power consumption using 60 mW @ 5V from a single power supply micro-
* *
* * *
* * * *
BLOCK DIAGRAM
DATA BUS BUFFER DTMF & TONE GENERATORS
AD0-AD7
8-BIT BUS FOR FSK MODULATOR/ DEMODULATOR
RD WR ALE CS RESET
READ WRITE CONTROL LOGIC
CONTROL AND STATUS
TRANSMIT FILTER RECEIVE FILTER
TXA
RXA
INT
STATUS AND CONTROL LOGIC
TXD RXD
SERIAL PORT FOR DATA
TESTS: ALB,DLB RDLB PATTERNS
SMART DIALING & DETECT FUNCTIONS
CLOCK GENERATOR
POWER
RXCLK
TXCLK CLK
EXCLK
GND XTL1 XTL2
VREF VDD ISET
73K321L CCITT V.23, V.21 Single-Chip
DESCRIPTION (continued)
The 73K321L is ideal for either free standing or integral system modem applications where multistandard data communications over the 2-wire switched telephone network is desired. Typical uses include videotex terminals, low-cost integral modems and built-in diagnostics for office automation or industrial control systems. The 73K321L's high functionality, low power consumption and efficient packaging simplify design requirements and increase system reliability in these applications. A complete modem requires only the addition of the phone line interface, a control microprocessor, and RS-232 level converter for a typical system. The 73K321L is part of TDK Semiconductor's K-Series family of pin and function compatible single-chip modem products. These devices allow systems to be configured for higher speeds and Bell or CCITT operation with only a single component change. OPERATION FSK MODULATOR/DEMODULATOR The FSK modulator produces a frequency modulated analog output signal using two discrete frequencies to represent the binary data. V.21 mode uses 980 and 1180 Hz (originate, mark and space) or 1650 and 1850 Hz (answer, mark and space). V.23 mode uses 1300 and 2100 Hz for the main channel and 390 and 450 Hz for the back channel. The modulation rate of the back channel is up to 75 baud. Demodulation involves detecting the received frequencies and decoding them into the appropriate binary value. PASSBAND FILTERS AND EQUALIZERS High and low band filters are included to shape the amplitude and phase response of the transmit and receive signals and provide compromise delay equalization and rejection of out-of-band signals in the receive channel. Amplitude and phase equalization are necessary to compensate for distortion of the transmission line and to reduce intersymbol interference in the bandlimited receive signal. AGC The automatic gain control maintains a signal level at the input to the demodulators which is constant to within 1 dB. It corrects quickly for increases in signal which would cause clipping and provides a total receiver dynamic range of >45 dB. PARALLEL BUS INTERFACE Four 8-bit registers are provided for control, option select and status monitoring. These registers are addressed with the AD0, AD1, and AD2 multiplexed address lines (latched by ALE) and appear to a control microprocessor as four consecutive memory locations. Two control registers and the tone register are read/write memory. The detect register is read only and cannot be modified except by modem response to monitored parameters. SERIAL CONTROL INTERFACE The Serial Command mode allows access to the 73K321L control and status registers via a serial command port. In this mode the AD0, AD1 and AD2 lines provide register addresses for data passed through the data pin under control of the RD and WR lines. A read operation is initiated when the RD line is taken low. The first bit is available after RD is brought low and the next seven cycles of EXCLK will then transfer out seven bits of the selected address location LSB first. A write takes place by shifting in eight bits of data LSB first for eight consecutive cycles of EXCLK. WR is then pulsed low and data transferred into the selected register occurs on the rising edge of WR. SPECIAL DETECT CIRCUITRY The special detect circuitry monitors the received analog signal to determine status or presence of carrier, answer tone and weak received signal (long loop condition). Special tones such as FSK marking and the 1300 Hz calling tone are also detected. A highly frequency selective call progress detector provides adequate discrimination to accurately detect European call progress signals. DTMF GENERATOR The DTMF generator will output one of 16 standard tone-pairs determined by a 4-bit binary value and TX DTMF mode bit previously loaded into the tone register. Dialing is initiated when the DTMF mode is selected using the tone register and the transmit enable (CR0 bit D1) is changed from 0 to 1.
2
73K321L CCITT V.23, V.21 Single-Chip Modem
PIN DESCRIPTION
POWER NAME GND VDD VREF ISET PLCC/DIP PIN NUMBER 28 15 26 24 TYPE I I O I DESCRIPTION System Ground. Power supply input, 5V 10%. Bypass with 0.1 and 22 F capacitors to GND. An internally generated reference voltage. Bypass with 0.1 F capacitor to GND. Chip current reference. Sets bias current for op-amps. The chip current is set by connecting this pin to VDD through a 2 M resistor. ISET should be bypassed to GND with a 0.1F capacitor.
PARALLEL MICROPROCESSOR CONTROL INTERFACE ALE AD0-AD7 CS 12 4-11 20 I I/O I Address latch enable. The falling edge of ALE latches the address on AD0-AD2 and the chip select on CS. Address/data bus. These bidirectional tri-state multi-plexed lines carry information to and from the internal registers. Chip select. A low during the falling edge of ALE on this pin allows a read cycle or a write cycle to occur. AD0-AD7 will not be driven and no registers will be written if CS (latched) is not active. The state of CS is latched on the falling edge of ALE. Output clock. This pin is the output of the crystal oscillator frequency only in the 73K321. Interrupt. This open drain output signal is used to inform the processor that a detect flag has occurred. The processor must then read the detect register to determine which detect triggered the interrupt. INT will stay low until the processor reads the detect register or does a full reset. Read. A low requests a read of the 73K321L internal registers. Data cannot be output unless both RD and the latched CS are active or low. Reset. An active high signal high on this pin will put the chip into an inactive state. All control register bits (CR0, CR1, Tone) will be reset. The output of the CLK pin will be set to the crystal frequency. An internal pull down resistor permits power on reset using a capacitor to VDD.
CLK INT
1 17
O O
RD
14
I
RESET
25
I
3
73K321L CCITT V.23, V.21 Single-Chip
PARALLEL MICROPROCESSOR CONTROL INTERFACE (continued) NAME WR PLCC/DIP PIN NUMBER 13 TYPE I DESCRIPTION Write. A low on this informs the 73K321L that data is available on AD0-AD7 for writing into an internal register. Data is latched on the rising edge of WR. No data is written unless both WR and the latched CS are low.
SERIAL MICROPROCESSOR CONTROL INTERFACE AD0-AD2 DATA (AD7) 4-6 11 I I/O Register Address Selection. These lines carry register addresses and should be valid during any read or write operation. Serial Control Data. Data for a read/write operation is clocked in or out on the falling edge of the EXCLK pin. The direction of data flow is controlled by the RD pin. RD low outputs data. RD high inputs data. Read. A low on this input informs the 73K321L that data or status information is being read by the processor. The falling edge of the RD signal will initiate a read from the addressed register. The RD signal must continue for eight falling edges of EXCLK in order to read all eight bits of the referenced register. Read data is provided LSB first. Data will not be output unless the RD signal is active. Write. A low on this input informs the 73K321L that data or status information has been shifted in through the DATA pin and is available for writing to an internal register. The normal procedure for a write is to shift in data LSB first on the DATA pin for eight consecutive falling edges of EXCLK and then to pulse WR low. Data is written on the rising edge of WR.
RD
14
I
WR
13
I
NOTE:
The Serial Control mode is provided by tying ALE high and CS low. In this configuration AD7 becomes DATA and AD0, AD1 and AD2 become the address only. See the Serial Control Timing diagrams on page 18
4
73K321L CCITT V.23, V.21 Single-Chip Modem
DTE USER INTERFACE NAME EXCLK RXCLK RXD PLCC/DIP PIN NUMBER 19 23 22 TYPE I O O/ Weak Pull-up O DESCRIPTION External Clock. Used for serial control interface to clock control data in or out of the 73K321L. Receive Clock. A clock which is 16 x1200, or 16 x 75 in V.23 mode, or 16 x 300 baud data rate is output in V.21. Received Digital Data Output. Serial receive data is available on this pin. The data is always valid on the rising edge of RXCLK when in Synchronous mode. RXD will output constant marks if no carrier is detected. Transmit Clock. TXCLK is always active. In V.23 mode the output is either a 16 x 1200 baud clock or 16 x 75 baud, in V.21 mode the clock is 16 x 300 baud. Transmit Digital Data Input. Serial data for transmission is input on this pin. In Asynchronous modes (1200 or 300 baud) no clocking is necessary.
TXCLK
18
TXD
21
I
ANALOG INTERFACE AND OSCILLATOR RXA TXA XTL1 XTL2 27 16 2 3 I O I I Received modulated analog signal input from the phone line. Transmit analog output to the phone line. These pins are for the internal crystal oscillator requiring an 11.0592 MHz Parallel mode crystal and two load capacitors to Ground. XTL2 can also be driven from an external clock.
5
73K321L CCITT V.23, V.21 Single-Chip
REGISTER DESCRIPTIONS
Four 8-bit internal registers are accessible for control and status monitoring. The registers are accessed in read or write operations by addressing the A0 and A1 address lines in Serial mode, or the AD0 and AD1 lines in Parallel mode. The AD0 and AD1 lines are latched by ALE. Register CR0 controls the method by which data is transferred over the phone REGISTER BIT SUMMARY line. CR1 controls the interface between the microprocessor and the 73K321L internal state. DR is a detect register which provides an indication of Monitored modem status conditions. TR, the tone control register, controls the DTMF generator; answer and guard tones and RXD output gate used in the modem initial connect sequence. All registers are read/write except for DR which is read only. Register control and status bits are identified below:
ADDRESS REGISTER CONTROL REGISTER 0 CONTROL REGISTER 1 DETECT REGISTER AD2 - AD0 D7 TRANSMIT MODE 4 D6 0 D5 TRANSMIT MODE 3 ENABLE DETECT INTERRUPT RECEIVE DATA TRANSMIT ANSWER TONE
DATA BIT NUMBER D4 TRANSMIT MODE 2 ADD PH. EQ. (V.23) D3 TRANSMIT MODE 1 CLK CONTROL D2 TRANSMIT MODE 0 D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
CR0
000
CR1
001
TRANSMIT PATTERN 1
TRANSMIT PATTERN 0
RESET
TEST MODE 1 CALL PROGRESS
TEST MODE 0 LONG LOOP
DR
010
X
X
X
CARRIER DETECT
SPECIAL TONE
TONE CONTROL REGISTER ID REGISTER
TR
011
RXD OUTPUT CONTROL
TRANSMIT CALLING TONE
TRANSMIT DTMF
DTMF3
DTMF2/ V.23 FDX
DTMF1
DTMF0/ ANSWER/SPEC. TONE SELECT
ID
110
ID
ID
ID
ID
X
X
X
X
NOTE:
When a register containing reserved control bits is written into, the reserved bits must be programmed as 0's. X = Undefined, mask in software
6
73K321L CCITT V.23, V.21 Single-Chip Modem
REGISTER ADDRESS TABLE
ADDRESS REGISTER AD2 - AD0 D7 D6 D5 DATA BIT NUMBER D4 D3 D2 D1 D0
CONTROL REGISTER 0
CR0
000
TRANSMIT MODE 4
0
TRANSMIT MODE 3
TRANSMIT MODE 2
0
TRANSMIT MODE 0
TRANSMIT ENABLE
ORIGINATE/ ANSWER
0=V.23 FSK 1=V.21 FSK
0000=PWR DOWN 0=DISABLE 1100=FSK TXA OUTPUT 0001=TRANSMIT DTMF, CALL PROGRESS DETECTION 1=ENABLE TXA OUTPUT
IN V.21 MODE: 0=ANSWER 1=ORIGINATE IN V.23 MODE : 0=RECEIVE @ 1200 BIT/S, TRANSMIT @ 75 BIT/S 1=RECEIVE @ 75 BIT/S, TRANSMIT @ 1200 BIT/S
CONTROL REGISTER 1
CR1
001
TRANSMIT PATTERN 1
TRANSMIT PATTERN 0
ENABLE DETECT INTERRUPT
ADD PH. EQ.
CLK CONTROL
RESET
TEST MODE 1
TEST MODE 0
00=TX DATA 01=TX ALTERNATE 10=TX MARK 11=TX SPACE
0=DISABLED 1=ENABLED
0=NORMAL EQ. 1=ADD EXTRA PHASE EQ. IN V.23
0=XTAL 0=NORMAL 00=NORMAL 1= NOT SUPPORTED IN THIS DEVICE 1=RESET 01=ANALOG LOOPBACK 10=REMOTE DIGITAL LOOPBACK 11=LOCAL DIGITAL LOOPBACK CARRIER DETECT SPECIAL TONE CALL PROGRESS LONG LOOP
DETECT REGISTER
DR
010
X
X
RECEIVE DATA
X
OUTPUTS RECEIVED DATA STREAM RXD OUTPUT CONTROL RXD PIN 0=NORMAL 1=TRI STATE
0=CONDITION NOT DETECTED 1=CONDITION DETECTED
TONE CONTROL REGISTER
TR
011
TRANSMIT CALLING TONE 0=OFF 1=ON
TRANSMIT ANSWER TONE 0=OFF 1=ON
TRANSMIT DTMF
DTMF3
DTMF2/ V.23 FDX
DTMF1
DTMF0/ SPECIAL TONE
0=DATA 1=TX DTMF
4 BIT CODE FOR 1 OF 16 DUAL TONE COMBINATIONS. OVERIDES OTHER TRANSMIT MODES 0=HALF DUPLEX V.23 1=ALLOWS V.23 FULL DUPLEX OPERATION
0=ANSWER TONE FREQ.=2225 Hz FSK MARK WILL BE INDICATED BY SPECIAL TONE BIT IN DR 1=ANSWER TONE FREQ.=2100 Hz EITHER 2100 Hz (IN ORIG.) OR 1300 Hz (IN ANS.) WILL BE INDICATED BY SPECIAL TONE BIT IN DR X X
ID REGISTER
10
110
ID
ID
ID
ID
X
X
00XX=73K212AL, 322L, 321L 01XX=73K221AL, 302L 10XX=73K222AL, 222BL 1100=73K224L 1110=73K324L 1100=73K224BL 1110=73K324BL
X = Undefined, mask in software 0 = Only write zero to these locations
7
73K321L CCITT V.23, V.21 Single-Chip
CONTROL REGISTER 0 D7 CR0 000 BIT NO. D0 TRANSMIT MODE 4 D6 0 D5 TRANSMIT MODE 3 D4 TRANSMIT MODE 2 D3 0 D2 TX DTMF D1 TRANSMIT ENABLE D0 ANSWER/ ORIGINATE
NAME Answer/ Originate
CONDITION 0
DESCRIPTION Selects Answer mode in V.21 (transmit in high band, receive in low band) or in V.23 mode, receive at1200 bit/s and transmit at 75 bit/s. Selects Originate mode in V.21 (transmit in low band, receive in high band) or in V.23 mode, receive at 75 bit/s and transmit at 1200 bit/s. If in V.23 and D2 of TR=1, selects V.23 full duplex operation in 4-wire configuration. Note: This bit works with TR bit D0 to program special tones detected in Tone Register. See detect and tone registers.
1
D1
Transmit Enable
0 1
Disables transmit output at TXA. Enables transmit output at TXA. Note: Answer tone and DTMF TX control require TX enable.
D7, D5, D4, D2
Transmit Mode
D7 0 0 0 1
D5 0 0 1 1
D4 D2 0 0 1 1 0 1 0 0 Power Down Transmit DTMF V.23 Mode V.21 Mode Not used; must be written as "0"
D6, D3
Unused
N/A
8
73K321L CCITT V.23, V.21 Single-Chip Modem
CONTROL REGISTER 1 D7 CR1 001 BIT NO. D1, D0 TRANSMIT PATTERN 1 D6 TRANSMIT PATTERN 0 NAME Test Mode D5 ENABLE DETECT INTER. CONDITION D1 0 0 D0 0 1 Selects Normal Operating mode. Analog Loopback mode. Loops the transmitted analog signal back to the receiver, and causes the receiver to use the same center frequency as the transmitter. To squelch the TXA pin, transmit enable must be forced low. Not used. Selects local digital loopback. Internally loops TXD back to RXD and continues to transmit data from TXA pin. Selects normal operation. Resets modem to power down state. All control register bits (CR0, CR1, Tone) are reset to zero. The output of the clock pin will be set to the crystal frequency. Not supported in the 73K321.See the TXCLK and RXCLK pin descriptions for 16x the data rate clocks. Selects normal equalization. In V.23 mode, additional phase equalization is added to the main channel filters when D4 is set to 1. Disables interrupt at INT pin. All interrupts are normally disabled in Power Down modes. Enables INT output. An interrupt will be generated with a change in status of DR bits D1-D3. The special tone and call progress detect interrupts are masked when the TX enable bit is set. Carrier detect is masked when TX DTMF is activated. All interrupts will be disabled if the device is in Power Down mode. D6 0 1 0 1 Selects normal data transmission as controlled by the state of the TXD pin. Selects an alternating mark/space transmit pattern for modem testing. Selects a constant mark transmit pattern. Selects a constant space transmit pattern. D4 ADD PH. EQ. D3 CLK CONTROL (WRITE 0) D2 RESET D1 TEST MODE 1 D0 TEST MODE 0
DESCRIPTION
1 1 D2 Reset 0 1
0 1
D3 D4
CLK Control (Clock Control) Add Ph. Eq.
Program as 0 0 1
D5
Enable Detect Interrupt
0 1
D7, D6
Transmit Pattern
D7 0 0 1 1
9
73K321L CCITT V.23, V.21 Single-Chip
DETECT REGISTER D7 DR 010 BIT NO. D0 D1 X D6 X NAME Long Loop Call Progress Detect D5 RECEIVE DATA CONDITION 0 1 0 1 D4 X D3 CARR. DETECT D2 SPECIAL TONE D1 CALL PROG. D0 LONG LOOP
DESCRIPTION Indicates normal received signal. Indicates low received signal level. No call progress tone detected. Indicates presence of call progress tones. The call progress detection circuitry is activated by energy in the normal 350 to 620 Hz call progress band when CR0 D2 =1. No special tone detected as programmed by CR0 bit D0 and Tone Register bit D0. Special tone detected. The detected tone is: (1) 2100 Hz answer tone if D0 of TR=1 and the device is in V.21 Originate mode. (2) 1300 Hz calling tone if D0 of TR=1 and the device is in V.21 or V.23 Answer mode. (3) an FSK mark for the mode the device is set to receive in if D0 of TR = 0. NOTE: Tolerance on special tones is 3%.
D2
Special Tone Detect
0 1
D3
Carrier Detect Unused Receive Data
0 1 Undefined
No carrier detected in the receive channel. Indicated carrier has been detected in the received channel. Not used in the 73K321L. Mask in software. Continuously outputs the received data stream. This data is the same as that output on the RXD pin, but it is not disabled when RXD is tri-stated.
D4 D5
D6, D7
Not Used
Undefined
Mask in software.
10
73K321L CCITT V.23, V.21 Single-Chip Modem
TONE REGISTER D7 TR 011 RXD OUTPUT CONTR. D6 TRANSMIT CALLING TONE NAME DTMF 0/ Answer Tone/ Special Tone/ Detect/Select X X X D5 TRANSMIT ANSWER TONE D4 TRANSMI T DTMF D3 DTMF 3 D2 DTMF 2/ V.234W/ FDX D1 DTMF 1 D0 DTMF 0/ ANS. TONE/ SPECIAL TONE/ SEL
BIT NO. D0
CONDITION D6 D5 D4 D0 X X X 1 0 0 X 0 1
DESCRIPTION D0 interacts with bits D6, D5, D4, and CR0 as shown. Transmit DTMF tones. Mark of an FSK mode selected in CR0 is to be detected in D2 of DR. 2100 Hz answer tone will be detected in D2 of DR if V.21 Originate mode is selected in CR0. 1300 Hz calling tone will be detected in D2 of DR if V.21 or V.23 Answer mode is selected in CR0.
X X D2 DTMF2/ V.23 4W/FDX
1 1 CR0
0 0
0 1
Transmit 2225 Hz answer tone in Answer mode. Transmit 2100 Hz answer tone in Answer mode.
TR D7 D5 D4 D2 D2 0 0 1 1 1 1 0 0 0 1 2-wire half duplex 4-wire full duplex Programs 1 of 16 DTMF tone pairs that will be transmitted when TX DTMF (TR bit D4) and TX enable bit (CR0, bit D2) are set. Tone encoding is shown below: KEYBOARD EQUIVALENT 1 2 3 4 5 6 7 8 9 0 DTMF CODE D3 D2 D1 D0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 TONES LOW 697 697 697 770 770 770 852 852 852 941 HIGH 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336
D3 D2 D3, D2, D1, D0 DTMF 3, 2, 1, 0 0 1 0 1
D1 D0 0 1 0- 1
11
73K321L CCITT V.23, V.21 Single-Chip
TONE REGISTER (continued) BIT NO. D3, D2, D1, D0
(continued)
NAME
CONDITION
DESCRIPTION KEYBOARD EQUIVALENT * # A B C D DTMF CODE D3 D2 D1 D0 1 1 1 1 1 0 0 1 1 1 1 0 1 0 0 1 1 0 1 0 1 0 1 0 TONES LOW HIGH 941 941 697 770 852 941 1209 1477 1633 1633 1633 1633
D4
Transmit DTMF
0 1
Disabled DTMF. Activates DTMF. The selected DTMF tones are transmitted continuously when this bit is high. TX DTMF overrides all other transmit functions. Disables answer tone generator. Enables answer tone generator. A 2100 Hz answer tone will be transmitted continuously when the transmit enable bit is set. The device must be in Answer mode. Disables calling tone generator. Transmit calling tone in either mode. Enables RXD pin. Receive data will be output on RXD. Disables RXD pin. The RXD pin reverts to a high impedance with internal weak pull-up resistor.
D5
Transmit Answer Tone
0 1
D6 D7
Transmit Calling Tone RXD Output Control
0 1 0 1
ID REGISTER ID 110 BIT NO. D7 ID NAME 0 0 1 1 1 1 1 D3-D0 Not Used D6 ID D5 ID CONDITION D7 D6 D7, D6, D5 D4 Device Identification Signature 0 1 0 1 1 1 1 D5 D4 X X X 0 1 0 1 X X X 0 0 0 0 D4 ID D3 X D2 X D1 X D0 X
DESCRIPTION Indicates Device: 73K212AL, 73K321L or 73K322L 73K221AL or 73K302L 73K222AL, 73K222BL 73K224L 73K324L 73K224BL 73K324BL Mask in software.
Undefined
12
73K321L CCITT V.23, V.21 Single-Chip Modem
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETER VDD Supply Voltage Storage Temperature Soldering Temperature (10 sec.) Applied Voltage RATING 7V -65 to 150C 260C -0.3 to VDD + 0.3V
NOTE: All inputs and outputs are protected from static charge using built-in, industry standard protection devices and all outputs are short-circuit protected. RECOMMENDED OPERATING CONDITIONS PARAMETER VDD Supply voltage TA, Operating Free-Air Temperature Clock Variation (11.0592 MHz) Crystal or external clock (External to GND) (Placed between VDD and ISET pins) (ISET pin to GND) (External to GND) (External to GND) Depends on crystal characteristics; from pin to GND CONDITION MIN 4.5 -40 -0.01 NOM 5 MAX 5.5 +85 +0.01 UNIT V C %
External Components (Refer to Application section for placement.) VREF Bypass Capacitor Bias setting resistor ISET Bypass Capacitor VDD Bypass Capacitor 1 VDD Bypass Capacitor 2 XTL1 Load Capacitor XTL2 Load Capacitor 0.1 1.8 0.1 0.1 22 40 20 2 2.2 F M F F F pF
13
73K321L CCITT V.23, V.21 Single-Chip
DC ELECTRICAL CHARACTERISTICS (TA = -40C to 85C, VDD = recommended range unless otherwise noted.) PARAMETER IDD, Supply Current IDDA, Active IDD1, Power-down IDD2, Power-down Digital Inputs VIH, Input High Voltage Reset, XTL1, XTL2 All other inputs VIL, Input Low Voltage IIH, Input High Current IIL, Input Low Current Reset Pull-down Current Input Capacitance Digital Outputs VOH, Output High Voltage VOL, Output Low Voltage VOL, CLK Output RXD Tri-State Pull-up Current CMAX, CLK Output IOH MIN = -0.4 mA IO MAX = 1.6 mA IO = 3.6 mA RXD = GND Maximum Capacitive Load -1 2.4 VDD 0.4 0.6 -50 15 V V V A pF VI = VIH Max VI = VIL Min Reset = VDD All Digital Input Pins -200 1 50 10 3.0 2.0 0 VDD VDD 0.8 100 V V V A A A pF CONDITION ISET Resistor = 2 M CLK = 11.0592 MHz CLK = 11.0592 MHz CLK = 19.200 kHz 8 12 4 3 mA mA mA MIN NOM MAX UNIT
14
73K321L CCITT V.23, V.21 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING (TA = -40C to +85C, VDD = Recommended range unless otherwise noted.) PARAMETER FSK Modulator Output Freq. Error Transmit Level Harmonic Distortion in 700-2900 Hz band Output Bias Distortion Total Output Jitter CLK = 11.0592 MHz Transmit Dotting Pattern THD in the alternate band FSK
Transmit Dotting Pattern in ALB @ RXD
CONDITION
MIN -0.35 -11.5
NOM
MAX +0.35
UNIT % dBm0 dB %
-10 -60 3
-9 -50
Random Input in ALB @ RXD
-10
+10
%
NOTE: Parameters expressed in dBm0 refer to the following definition: 0 dB loss in the Transmit path from TXA to the telephone line. 2 dB gain in the Receive path from the telephone line to RXA. Refer to the Basic Box Modem diagram in the Applications section for the DAA design. DTMF Generator Frequency Accuracy Output Amplitude Output Amplitude Twist Long Loop Detect Dynamic Range Call Progress Detector Detect Level Reject Level Delay Time Hold Time Hysteresis Carrier Detect Threshold Delay Time V.21 V.23 Forward Channel V.23 Back Channel Hold Time V.21 V.23 Forward Channel V.23 Back Channel Hysteresis 6 3 10 2 20 8 25 ms ms ms dB 10 6 25 20 12 40 ms ms ms Single Tone -48 -43 dBm0 -3 dB points in 285 and 675 Hz Test signal is a 460 Hz sinusoid -70 dBm0 to -30 dBm0 STEP -30 dBm0 to -70 dBm0 STEP 2 -38 -45 40 40 dBm0 dBm0 ms ms dB Low Band, CR0 bit D2=1 High Band, CR0 bit D2=1 High-Band to Low-Band, as above Not valid for V.23 back channel Refer to Performance Curves -0.25 -10 -8 1.0 -38 43 -9 -7 2.0 +0.25 -8 -6 3.0 -28 % dBm0 dBm0 dB dBm0 dB
15
73K321L CCITT V.23, V.21 Single-Chip
DYNAMIC CHARACTERISTICS AND TIMING (continued) PARAMETER Special Tone Detectors Detect Level Delay Time 2100 Hz answer tone 1300 Hz calling tone 390 Hz V.23 back channel mark 980 or 1650 Hz V.21 marks Hold Time 2100 Hz answer tone 1300 Hz calling tone 390 Hz V.23 back channel mark 980 or 1650 Hz V.21 marks Hysteresis Detect Freq. Range Output Smoothing Filter Output load TXA pin; FSK Single Tone out for THD = -50 dB in 0.3 to 3.4 kHz Out of Band Energy Output Impedance Clock Noise Frequency >12 kHz in all modes TXA pin, TXA Enabled TXA pin; 76.8 kHz or 122.88 kHz in V.23 main channel 20 0.1 -60 50 0.4 dBm0 mVrms 10 50 k pF Any Special Tone -30 dBm0 to -70 dBm0 Step 4 3 10 5 2 -3 +3 15 10 25 15 ms ms ms ms dB % See definitions for TR bit D0 mode -70 dBm0 to -30 dBm0 Step 10 10 20 10 25 25 65 25 ms ms ms ms -48 -43 dBm0 CONDITION MIN NOM MAX UNIT
16
73K321L CCITT V.23, V.21 Single-Chip Modem
DYNAMIC CHARACTERISTICS AND TIMING PARALLEL CONTROL INTERFACE PARAMETER Timing (Refer to Timing Diagrams) TAL TLA TLC TCL TRD TLL TRDF TRW TWW TDW TWD CS ADDR CS setup before ALE Low ADDR hold after ALE Low CS/ADDR hold after ALE Low ALE Low to RD/WR Low RD/ WR Control to ALE High Data out from RD Low ALE width Data float after RD High RD width WR width Data setup before WR High Data hold after WR High 200 140 40 25 30 90 15 25 20 30 -5 140 ns ns ns ns ns ns ns ns ns ns ns ns CONDITION MIN NOM MAX UNIT
NOTE: Asserting ALE, CS, and RD or WR concurrently can cause unintentional register accesses. When using non-8031 compatible processors, care must be taken to prevent this from occurring when designing the interface logic.
BUS TIMING DIAGRAM (PARALLEL CONTROL MODE)
TLL ALE TLC RD WR TLA TAL AD0-AD7 CS ADDRESS READ DATA ADDRESS TRD TRDF TDW WRITE DATA TWD TRW TCL TLC TWW
17
73K321L CCITT V.23, V.21 Single-Chip
DYNAMIC CHARACTERISTICS AND TIMING SERIAL CONTROL INTERFACE PARAMETER Timing (Refer to Timing Diagrams) TWW TRD TRDF TCKD TCKW TDCK TAC TCA TWH * WR width Data out from RD Low Data float after RD High Data out after EXCLK Low WR after EXCLK Low Data setup before EXCLK Low Address setup before control* Address hold after control* Data Hold after EXCLK 200 150 50 50 85 140 25000 140 50 200 ns ns ns ns ns ns ns ns ns CONDITION MIN NOM MAX UNIT
Control for setup is the falling edge of RD or WR. Control for hold is the falling edge of RD or the rising edge of WR. READ TIMING DIAGRAM (SERIAL CONTROL MODE)
EXCLK
RD TAC AD0-AD2 TCA
ADDRESS
TRD AD7 D0 D1
TCKD D2 D3 D4 D5 D6 D7
TRDF
Note: EXCLK must be low to read D0 after RD is asserted WRITE TIMING DIAGRAM (SERIAL CONTROL MODE)
EXCLK
TWW WR TCKW TAC TCA AD0-AD2 ADDRESS TDCK AD7 D0 D1 D2 D3 D4 D5 D6 D7
TWH
18
73K321L CCITT V.23, V.21 Single-Chip Modem
APPLICATIONS INFORMATION
GENERAL CONSIDERATIONS Figures 1 and 2 show basic circuit diagrams for K-Series modem integrated circuits. K-Series products are designed to be used in conjunction with a control processor, a UART or RS-232 serial data interface, and a DAA phone line interface to function as a typical intelligent modem. The K-Series ICs interface directly with Intel 8048 and 80C51 microprocessors for control and status monitoring purposes.Two typical DAA arrangements are shown: one for a split 5 or 12 volt design and one for a single 5 volt design. These diagrams are for reference only and do not represent productionready modem designs.
C14 39 pF Y1 11.0592 MHZ C13 18 pF +5V
K-Series devices are available with two control interface versions: one for a parallel multiplexed address/data interface, and one for a serial interface. The parallel version is intended for use with 8039/48 or 8031/51 microcontrollers from Intel or many other manufacturers. The serial can be used with other microcontrollers or in applications where only a limited number of port lines are available or the application does not lend itself to a multiplexed address/data interface. The parallel versions may also be used in the Serial mode, as explained in the data sheet pin description. In most applications the controller will monitor the serial data for commands from the DTE and the received data for break signals from the far end modem. In this way, commands to the modem are sent over the same line as the transmitted data. In other applications the RS-232 interface handshake lines are used for modem control.
+
N/C
R10 2.2M XTL1 INT CLK INT AD7:0 RD WR ALE CS RXA K-SERIES LOW POWER FAMILY C6 0.1 F RXA XTL1 XTL2 VDD ISET GND VREF C10 0.1 F C11 0.1 F C9 0.1 F
RS232 LEVEL CONVERTERS CA CB CC CD CF RTS CTS DSR DTR DCD
XTL2 80C51 P1.0 P1.1 P1.2 P1.3 P1.5 P1.6
C8 22 F
C1 390 pF
P0.0-7 RD WR ALE P3.1 P3.2
R5 37.4K R4 20K LM 1458 U1A C2 300 pF R7 43.2K R6 20K C3 1000 pF
R4 5.1K R3 3.6K
+
P3.0 P1.7 RESET BA BB DA DD DB U5, U6 MC145406 TXD RXD EXCLK RXCLK TXCLK
TXA C7 0.1 F RESET TXA +5V C12 1 F
V+ LM 1458
-
R1 U1B V- 475 1% D3, D4 4.7V ZENER C4 0.033 F
T1 MIDCOM 671-8005 C5 0.47 F 250V U2 4N35 D1 IN4004 +5V K1 D2 IN914 R9 10K +5 R8 22K
+
T
VR1 MOV V250L20
R Q1 2N2222A
22K
FIGURE 1: Basic Box Modem with Dual-Supply Hybrid
19
73K321L CCITT V.23, V.21 Single-Chip
DIRECT ACCESS ARRANGEMENT (DAA) The telephone line interfaces show two examples of how the "hybrid" may be implemented. The split supply design (Figure 1) is a typical two op-amp hybrid. The receive op-amp serves two purposes. It supplies gain to amplify the receive signal to the proper level for the modem's detectors and demodulator, and it removes the transmitted signal from the receive signal present at the transformer. This is done by supplying a portion of the transmitted signal to the non-inverting input of the receive op-amp at the same amplitude as the signal appearing at the transformer, making the transmit signal Common mode. The single-supply hybrid is more complex than the dual-supply version described above, but its use eliminates the need for a second power supply. This circuit (Figure 2) uses a bridged drive to allow undistorted signals to be sent with a single 5V supply.
C1 390 pF
Because DTMF tones utilize a higher amplitude than data, these signals will clip if a single-ended drive approach is used. The bridged driver uses an extra op-amp (U1A) to invert the signal coming from the gain setting op-amp (U1B) before sending it to the other leg of the transformer. Each op-amp then supplies half the drive signal to the transformer. The receive amplifier (U1C) picks off its signal at the junction of the impedance matching resistor and the transformer. Because the bottom leg of the transformer is being driven in one direction by U1A and the resistor is driven in the opposite direction at the same time by U1B, the junction of the transformer and resistor remains relatively constant and the receive signal is unaffected. DESIGN CONSIDERATIONS TDK Semiconductor's 1-chip modem products include all basic modem functions. This makes these devices adaptable for use in a variety of applications, and as easy to control as conventional digital bus peripherals.
R4 37.4K 1% C3 0.1 F RXA C4 0.0047 F R1 20K 1%
8
* U1C
9
10 +
R2 20K 1%
R5 3.3K
* Note: Op-amp U1 must be rated for single 5V operation. R10 & R11 values depend on Op-amp used.
+5V 5 6
+ -
4 7 11
R3 475 1% T1 MIDCOM 671-8005 T C10 0.47 F 250V C2 0.033 F U2 4N35 D1 IN4004 R13 22K +5V
* U1B
R6 22.1K C6 0.1 F TXA R9 20K 1% R8 20K 1% 2 3 +5V VOLTAGE REFERENCE K1 R10* D4 IN914 R7 20K 1% C5 750 pF
D2 3.3V ZENERS D3 1 +5V
VR1 MOV V250L20
R12 22K
- * U1A +
R R14 10K Q1 2N2222A
R11*
C7 0.1 F
+
C8 10 F
HOOK RING
FIGURE 2: Single 5V Hybrid Version
20
73K321L CCITT V.23, V.21 Single-Chip Modem
Unlike digital logic circuitry, modem designs must properly contend with precise frequency tolerances and very low level analog signals, to ensure acceptable performance. Using good analog circuit design practices will generally result in a sound design. Following are additional recommendations which should be taken into consideration when starting new designs. CRYSTAL OSCILLATOR The K-Series crystal oscillator requires a Parallel mode (antiresonant) crystal which operates at 11.0592 MHz. It is important that this frequency be maintained to within 0.01% accuracy. In order for a Parallel mode crystal to operate correctly and to specification, it must have a load capacitor connected to the junction of each of the crystal and internal inverter connections, terminated to ground. The values of these capacitors depend primarily on the crystal's characteristics, and to a lesser degree on the internal inverter circuit. The values used affect the accuracy and start up characteristics of the oscillator. LAYOUT CONSIDERATIONS Good analog/digital design rules must be used to control system noise in order to obtain highest performance in modem designs. The more digital circuitry present on the PC board, the more this attention to noise control is needed. The modem should be treated as a high impedance analog device. A 22 F electrolytic capacitor in parallel with a 0.1 F ceramic capacitor between VDD and GND is recommended. Liberal use of ground planes and larger traces on power and ground are also highly favored. High speed digital circuits tend to generate a significant amount of EMI (Electro-Magnetic Interference) which must be minimized in order to meet regulatory agency limitations. To accomplish this, high speed digital devices should be locally bypassed, and the telephone line interface and K-Series device should be located close to each other near the area of the board where the phone line connection is accessed. To avoid problems, power supply and ground traces should be routed separately to the analog and digital functions on the board, and digital signals should not be routed near low level or high impedance analog traces. The analog and digital grounds should only connect at one point near the K-Series device ground pin to avoid ground loops. The K-Series modem IC's should have both high frequency and low frequency bypassing as close to the package as possible.
MODEM PERFORMANCE CHARACTERISTICS
The curves presented here define modem IC performance under a variety of line conditions while inducing disturbances that are typical of those encountered during data transmission on public service telephone lines. Test data was taken using an AEA Electronics' "Autotest I" modem test set and line simulator, operating under computer control. All tests were run full-duplex, using a Concord Data Systems 224 as the reference modem. A 511 pseudo-random-bit pattern was used for each data point. Noise was C-message weighted and all signal-to-noise (S/N) ratios reflect total power measurements similar to the CCITT V.56 measurement specification. The individual tests are defined as follows. BER vs. S/N This test measures the ability of the modem to operate over noisy lines with a minimum of datatransfer errors. Since some noise is generated in the best of dial-up lines, the modem must operate with the lowest S/N ratio possible. Better modem performance is indicated by test curves that are closest to the BER axis. A narrow spread between curves representing the four line parameters indicates minimal variation in performance while operating over a range of aberrant operating conditions. Typically, a DPSK modem will exhibit better BER-performance test curves receiving in the low band than in the high band. BER vs. Receive Level This test measures the dynamic range of the modem. Because signal levels vary widely over dialup lines, the widest possible dynamic range is desirable. The minimum Bell specification calls for 36 dB of dynamic range. S/N ratios are held constant at the indicated values while the receive level is lowered from a very high to very low signal levels. The width of the "bowl" of these curves, taken at the BER point, is the measure of dynamic range.
21
73K321L CCITT V.23, V.21 Single-Chip
73K321L BER vs SIGNAL TO NOISE
10 -2
V.21 OPERATION -40 dBM
73K321L BER vs RECEIVE LEVEL (V.23)
10 -2
V.23 MAIN CHANNEL RECEIVE OPERATION C2 LINE, S/N = 9.5 dB
FLAT HIGH BAND
10 -3
C2 HIGH BAND
10 -3
BIT ERROR RATE
BIT ERROR RATE
10 -4
10 -4
3002 HIGH BAND
10 -5
10 -5
LOW BAND RECEIVE FLAT, 3002, AND C2 LINES
10
-6
10 -6
0 1 2 3 4 5 6 7 8 9 10 11 12
10
0
-10
-20
-30
-40
-50
SIGNAL TO NOISE (dB)
RECEIVE LEVEL (dB)
73K321L BER vs S/N (V.23 ONLY)**
10 -2
V.23 OPERATION -40 dBM
*
=
"EQ On" Indicates bit CR1 D4 is set for additional phase equalization. 73K302L performance is similar to that of the 73K322L. V.23 operation corresponds to Bell 202.
** =
C2 EQ. OFF
3002 EQ. OFF
10 -3
3002 EQ. ON
BIT ERROR RATE
FLAT EQ. OFF
10 -4
BACK CHANNEL
FLAT EQ. ON
10 -5
C2 EQ. ON
10
-6
-2
0
2
4
6
8
10
12 14
16 18
20 22
SIGNAL TO NOISE (dB)
22
73K321L CCITT V.23, V.21 Single-Chip Modem
MECHANICAL SPECIFICATIONS
28-Pin DIP
28-Pin PLCC
23
73K321L CCITT V.23, V.21 Single-Chip
PACKAGE PIN DESIGNATIONS
(TOP VIEW)
CAUTION: Use handling procedures necessary for a static sensitive component.
CLK XTL1 XTL2 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 ALE WR RD
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
GND RXA VREF RESET ISET RXCLK RXD TXD CS EXCLK TXCLK INT TXA VDD
5 6 7 8 9 10 11 4 3 2 1 28 27 26 25 24
PLCC PINOUTS ARE THE SAME AS THE 28-PIN DIP
23 22 21 20 19
12 13
14
15 16
17
18
600-Mil 28-Pin DIP 73K321L-IP
28-Pin PLCC 73K321L-IH
ORDERING INFORMATION PART DESCRIPTION 73K321L 28-Pin 5V Supply Plastic Dual-In-Line Plastic Leaded Chip Carrier 73K321L-IP 73K321L-IH 73K321L-IP 73K321L-IH ORDER NO. PKG. MARK
No responsibility is assumed by TDK Semiconductor Corporation for use of this product nor for any infringements of patents and trademarks or other rights of third parties resulting from its use. No license is granted under any patents, patent rights or trademarks of TDK Semiconductor Corporation and the company reserves the right to make changes in specifications at any time without notice. Accordingly, the reader is cautioned to verify that you are referencing the most current data sheet before placing orders. To do so, see our web site at http://www.tsc.tdk.com or contact your local TDK Semiconductor representative. TDK Semiconductor Corp., 2642 Michelle Dr., Tustin, CA 92780, (714) 508-8800, FAX (714) 508-8877, http://www.tdksemiconductor.com 04/24/00 - rev. E Protected by the following patents: (4,691,172) (4,777,453) (c)1989 TDK Semiconductor Corporation
24

▲Up To Search▲

Price & Availability of 73K321L-IH

	To Download 73K321L-IH Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .